Several power saving modes for whole chip and host controller , and suspend mode for peripheral controller 整個芯片和主機(jī)控制器的多種功率節(jié)約模式,以及外圍設(shè)備的延緩模式。
The full speed peripheral controller is very flexible and software configurable , in terms of the type , size , and buffering mechanism of each endpoint 就每一個終端的類型,大小和緩沖機(jī)構(gòu)而言,全速處理器非常靈活,而且其軟件可設(shè)置。
The ep2s15 of altera company , work as the system ’ s peripheral controller include fifo ( first in first out ) memory and sampling clock controller Altera公司的ep2s15作為系統(tǒng)的外圍控制器,實(shí)現(xiàn)對系統(tǒng)的fifo (先進(jìn)先出存儲器)與采樣時鐘的控制。
A device or section of a device ( say , of a peripheral controller ) used to initialize magnetic discs and , often , to perform transferrelated functions 為初始化磁盤和常常執(zhí)行與傳送相關(guān)的功能所使用的一種裝置或一種裝置的一部分(如外設(shè)控制器的一部分) 。
The peripheral controller consists of frequency detector , data sample controller , fifo , lcd driver and the interface circuit between dsp and fpga 外圍控制器囊括了硬件系統(tǒng)中幾乎所有的數(shù)字電路,包括頻率/周期測量、數(shù)據(jù)采集控制、 fifo 、 lcd驅(qū)動以及fpga與dsp之間的接口電路等。